A PLD is a semiconductor integrated circuit that contains logic circuitry that can be programmed (“designed”) by a user to perform a host of logic functions. An FPGA is an example of a PLD that may benefit from the presently disclosed system design tools and techniques. The assignee of the present invention develops and manufactures PLDs including those that incorporate embedded processors, and complex programmable logic devices (CPLDs). These semiconductor integrated circuits, or chips, may be designed by a purchaser (“user”) for use in the user's own electronic systems.
Normally, reconfiguring a designed PLD requires the PLD user to place the PLD in a reset mode while a controller is used to load a different design onto it. “Partial reconfiguration” of a PLD, as the term is used herein and in the claims, means making a change to a portion of a PLD while at least one other portion is still operating. Partial reconfiguration allows for some parts of the designed PLD to continue operating while a controller loads a partial design into another portion of the PLD. The controller may be within an operating portion of the PLD or within an external component.
Partial reconfiguration provides various benefits to the user, including reduction in the size, cost, and power consumption of the PLD and improved fault tolerance/reliability. For example, using a partial reconfiguration technique permits selectively powering down parts of a PLD, while the remainder of the PLD continues to operate normally. As a further example, a partial reconfiguration technique may be used to simulate a single event upset (SEU) so that a designer is enabled to test a response of a PLD design to various possible SEU events. Moreover, if an SEU event causes data corruption that cannot be cured by rewriting the corrupted data, a partial reconfiguration technique may be used to isolate the damaged portion of the PLD, while the remainder of the PLD continues to operate normally.
In the absence of the present teachings, it is a difficult and error-prone task for a user to develop a PLD design capable of partial reconfiguration. The present disclosure provides a set of system-level techniques and design tools that make developing a PLD design intended to support partial reconfiguration relatively more efficient.